`timescale 1ns / 1ps
//Name: Robert Smith
//PID: A08609119
//Name: Shreenidhi Chowkwale
//PID: A09089080
module pc_compute#(parameter D_WIDTH = 34, I_WIDTH = 17, SWTCH_OFFSET = 4, A_WIDTH = 10)
(
	input [D_WIDTH - 1 : 0] regfile_output_i,
	input [I_WIDTH - 1 : 0] label_i,
	input [A_WIDTH - 1 : 0] pc_i,
	input is_swtch_i,
	input has_lab_or_imm_i,
	input uses_label_i,
	input is_swtch_or_jr_i,
	input branch_taken_i,
	output [A_WIDTH - 1: 0] pc_o
);	
	wire [A_WIDTH - 1 : 0] pc_plus_one;
	wire [A_WIDTH - 1 : 0] pc_plus_four;
	wire [A_WIDTH - 1 : 0] pc_swtch_offset;
	
	reg [A_WIDTH - 1 : 0] lab_or_imm_mux, uses_label_mux, is_swtch_mux, is_swtch_or_jr_mux, branch_taken_mux;
	
	assign pc_plus_one = pc_i + 1;
	assign pc_plus_four = pc_i + 4;
	assign pc_swtch_offset = pc_plus_one + (regfile_output_i[A_WIDTH - 1 : 0] << SWTCH_OFFSET);
	
	reg [A_WIDTH - 1 : 0] pc_next;
    	      
	always_comb
		begin
			if(has_lab_or_imm_i)
				lab_or_imm_mux = pc_plus_four;
			else
				lab_or_imm_mux = pc_plus_one;
			if(uses_label_i)
				uses_label_mux = label_i[A_WIDTH - 1:0];
			else
				uses_label_mux = lab_or_imm_mux;
			if(is_swtch_i)
				is_swtch_mux = pc_swtch_offset;
			else
				is_swtch_mux = regfile_output_i[A_WIDTH - 1:0];
			if(is_swtch_or_jr_i)
				is_swtch_or_jr_mux = is_swtch_mux;
			else
				is_swtch_or_jr_mux = uses_label_mux;
			if(branch_taken_i | is_swtch_i)
				pc_next = is_swtch_or_jr_mux;
			else
				pc_next = lab_or_imm_mux;
				
		end
    
	assign pc_o = pc_next;    

endmodule
